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GaAs MANTecH On-Line Search
Search our On-Line Digest Paper Abstract pages.
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The
International Conference on
Compound Semiconductor Manufacturing Technology
"Sharing Ideas Throughout the
Industry"
2003 On-line
Digest Table of Contents
Order
everything you need with our convenient
on-line
order form,
or contact Margaret
Doyle at mdoyle@gaasmantech.org
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Full document in PDF format |
View |
| 1.1 |
The four
key development vectors for next-generation handset design
David
J. Aldrich,
Skyworks
Solutions Inc. |
Abstract |
|
1.2 |
A DARPA Perspective on the Future of
Electronics
John C. Zolper,
DARPA/MTO |
Abstract
|
1.3
|
GaAs
and SiGec BiCMOS
Cost Comparison – Is SiGec Always
Cheaper?
Mark Wilson, Motorola Semiconductor Products
Sector |
|
2.1
|
Advance
in Compound Semiconductor of China
Qi Huang and Junming Zhou, Institute of
Physics, Chinese Academy of Sciences, Advanced Chinese Epitaxy Ltd. |
|
2.2
|
RF Power
Amplifiers for Cellphones
C.E. Weitzel,
Motorola, Inc., Semiconductor Products Sector |
|
2.3
|
Ultra
Broadband MEMS Switch on Silicon and GaAs
Substrates
Richard Chan, Robert
Lesnick, David Caruth, and Milton
Feng, High Speed Integrated Circuits
Group, Department of Electrical and Computer Engineering, University
of Illinois |
|
2.4
|
Root
Cause Analysis and Reduction of Off-State Leakage Current to
Increase Manufacturability of a HIGFET Device
J.
Hughes, E. Huang, J. Apibunyopas, C.
Della-Morrow, T. Nilsson, M. Coe, Motorola Semiconductor Products
Sector |
|
3.1
|
Impact of
Substrate Imperfections on Epitaxial
Layer Quality
Michael Wojtowicz, Randy
Sandhu, Ben Heying,
and Thomas Block, Northrop Grumman Space Technology |
|
3.2
|
Use of Re-etched and Re-polished
Epi-wafers for MBE Calibration Substrates
J. Lowmaster, R. Pelzel, M. Dydyk, D. Green,
IQE, Inc., |
|
3.3
|
Commercial Production of Large Diameter InP-HBT Epiwafers by MBE
D. I.
Lubyshev, K. Teker, O. Malis, Y. Wu, J. M. Fastenau, X.-M. Fang, C.
Doss, A. B. Cornfeld, and W. K. Liu, IQE Inc., |
|
3.4
|
Volume
Epitaxial Growth of Enhanced Mode
HIGFETs using Minimal Material
Characterization and Rapid Inline Processing to Minimize Risk
Michael Pelczynski, Mark
Rittgers, Bob
Duffin, Celicia Della-Morrow,
Mikhail Mikhov*, Motorola Inc.
Semiconductor Product Sector |
|
|
3.5 |
Active Carbon Control
During VGF Growth of Semiinsulating
GaAs
T.
Bünger, J.
Stenzenberger, F. Börner, U.
Kretzer, S. Eichler,
M. Jurisch, R.
Bindemann, B. Weinert, S.
Teichert, T. Flade,
Freiberger
Compound Materials GmbH |
Abstract |
4.1
|
MIM’s
the Word – Capacitors for Fun and Profit
Martin
J. Brophy, Alfredo
Torrejon, Shawn Petersen, Kamal
Avala, and Li Liu,
TriQuint
Semiconductor |
|
4.2
|
On the
Development of High Density Nitrides for
MMICs
Y. C. Chou, R. Lai, G. P. Li , H.
Guan * , R. Grundbacher, P. Nam, H. K.
Kim, Y. Ra ** , M. Barsky, M.
Biedenbender, and A. Oki, Northrop
Grumman Space Technology |
|
4.3
|
Development and Characterization of a 600 Å PecVD Si3N4 High-Density
MIM Capacitor for InGaP/GaAs HBT
Applications
Jiro
Yota,
Ravi
Ramanathan, Jose
Arreaga, Peter Dai, Cristian
Cismaru, Richard Burton,
Parminder Bal,
Lance Rushing,
Skyworks
Solutions, Inc. |
|
4.4
|
Characteristics of Low-k Film Deposited by Plasma-Enhanced CVD Using
a Liquid BCB Source
Suehiro
Sugitani, Hideaki
Matsuzaki, and Takatomo
Enoki, NTT Photonics Laboratories,
NTT Corporation |
|
4.5
|
Metal
particle effects on thin film capacitors in high volume
manufacturing
Muralidhar R. Rao, Sheila T. O'Neil, Shiban
Tiku, Skyworks Solutions Inc., |
|
4.6
|
Backside
Emission Microscopy Applications In
Compound Semiconductor Manufacturing Debug
P. Sanders, H. Henry, D. Hill, M.
Sadaka, S. Wilson, Motorola
Semiconductor Products Sector |
|
5.1
|
Compact
System-on-Package (SOP) Architectures
for
low cost RF Front-end modules
J. Laskar, S.
Pinel, K. Lim, A.
Raghavan, R. Li, C-H. Lee, M. Maeng,
M.F. Davis, M. Tentzeris.,
School of ecE, Georgia Institute of
Technology |
|
5.2
|
Integrated circuits using embedded III-V-on-Ge MHEMTs in multi-layer
thin-film technology
R. Vandersmissen 1 , D. Schreurs 1 , S.
Vandenberghe 1 , G. Carchon, and G. Borghs 2, IMec, MCP, |
|
5.3
|
Wafer-Level Assembly of Heterogeneous Technologies
J.-Q. Lu, A. Jindal,
P.D. Persans, T.S.
Cale, and R.J. Gutmann,
Interconnect Focus Center: Interconnections for
Gigascale Integration, Rensselaer Polytechnic Institute |
|
5.4
|
Dense,
Two-Dimensional Optoelectronic Chips for High-Speed, Parallel
Optical Links
Doug J. Burrows, Kelly A. Zabierek, Richard R.
Dennis, Suzanne M. Wade, and Robert W. Cook, TeraConnect, Inc.,
|
|
5.5
|
Power
GaInP/GaAs HBTs
for High Voltage Operation
P. Kurpas, A.
Maaßdorf, W. Doser*,
W. Köhler, P.
Heymann, B. Janke, F.
Schnieder, H.
Blanck*, P. Auxemery**, D.
Pons**, W. Heinrich, J.
Würfl, Ferdinand-Braun-Institut
für
Höchstfrequenztechnik (FBH) |
|
6.1
|
Refractory Gate Metallization Characterization for HIGFET Power
Amplifiers
James Cotronakis,
Thomas Nilsson, Motorola Compound Semiconductor |
|
6.2
|
Fabrication and Characterization of Thin Film Resistors for
GaAs-Based
Power Amplifiers
Hong Shen, Jose
Arreaga,
Ravi
Ramanathan, Heather
Knoedler, John Sawyer, and Shiban
Tiku,
Skyworks
Solutions, Inc., |
|
6.3
|
NiGeAu
Ohmic Contact in
InGaP pHEMTs
Ellen Lan,
Qianghua Xie,
Peter Fejes, and Ha Le, Motorola Inc.,
Semiconductor Products Sector |
|
6.4
|
Advances
in Gold Metallization at Motorola's Compound Semiconductor Fab (CS1)
Chad M. Becker, William Rummel*, Dr. Paul
Ocansey, Motorola Compound Semiconductor |
|
6.5
|
The Study
of Dendrites Formation Mechanism to Enhance Gold Plating Process
Yield, Throughput, and Solution Lifetime
S.J. Huang, H.C. Chou, T.C. Lee, B. Lin, D.W.
Tu, P.C. Chao, and C.S. Wu, WIN
Semiconductors Corporation |
|
7.1
|
High
Voltage Microwave Devices: An Overview
D. Miller and M. Drinkwine, M/A-COM,
Inc. |
|
7.2
|
III-V
Compound Semiconductor Industry and Technology Development in Taiwan
Yung S. Liu,
Optoelectonics
& Systems Laboratories, Industrial Technology Research Institute |
|
7.3
|
High
Speed 0.18µm Ion-implanted GaAs MESFET
Process with High Uniformity & Excellent Reproducibility
D. Fukushi, M.
Watanabe and S. Nakajima, Optoelectronics R&D Laboratories, Sumitomo
Electric Ind., Ltd. |
|
7.4
|
Deterministic Process Control Using a Multivariate Model
D. Miller, M/A-COM, Inc. |
|
7.5
|
Trade-off
Relationship between Breakdown and Gate-Lag in Recessed-Gate
GaAs
FETs
Y. Mitani, D. Kasai and K.
Horio, Faculty of Systems Engineering,
Shibaura Institute of Technology |
|
8.1
|
Optimization of PHEMT for Microwave Power Applications
T. Baksht, S.
Solodky, A.
Khramtsov, * S. Hava * and
Yoram Shapira,
Faculty of Engineering,Tel
Aviv
University,Ramat
Aviv,69978,Israel; Engineering Faculty,Ben-Gurion
University of the
Negev,
Mark Leibovich
and Gregory Bunin Gal El (MMIC) |
|
8.2
|
The First
0.15um MHEMT 6”GaAs Foundry Service: Highly Reliable Process for 3 V
Drain Bias Operations
M. Chertouk, W. D.
Chang, C. G. Yuan, H. H. Chen, L. Lo, C. H. Chen, D. W.
Tu, J. Liu, N.
Draidia, P. C. Chao, WIN
Semiconductors Corp. |
|
8.3
|
High
Power Ka – Band PIN Diode Technology
B. Houli-Arbiv, G. Bunin, J. Kaplun, I.
Hallakoun, T. Boterashvili, Y. Knafo, A. Cohen-Nov, M. Leibovitch,
B. Revzin, Gal-El (MMIC)
|
|
8.4
|
Predictive Modeling of InGaP/GaAs HBT
Noise Parameters from DC and S-Parameter Data for Wireless Power
Amplifier Design
James Chingwei Li
1 , Peter J.
Zampardi 2 , and Van Pho 3,
Skyworks Solutions Inc., |
|
8.5
|
Phase
Formation in Gold-Tin Alloys Electroplated from a Non-cyanide Bath
Yahui Zhang and Douglas G. Ivey, Department of
Chemical and Materials Engineering, University of Alberta |
|
8.6
|
Cycle
Time Reduction During Electroplating of Through Wafer Vias For
Backside Metallization of III-V Semiconductor Circuits
Dennis Anderson, Heather Knoedler, Shiban Tiku,
Skyworks Solutions Inc., |
|
8.7
|
Properties, process control, and characterization of PecVD silicon
nitrides for
compound
semiconductor devices
Candi
S. Cook,1,2 Terry Daly,1 Ran Liu,1
Michael Canonico,1 Martha Erickson,1 Qianghua
Xie,1 Rich Gregory,1 and Stefan
Zollner 1
1 Motorola, Inc., 2 Arizona State University, Science and
Engineering of Materials Program |
|
8.8
|
Characterization and Control of Galvanic Corrosion During GaAs Wafer
Photoresist Processing
J. Moore, H. Hendriks*, and A. Morales*,
General Chemical - Electronic Materials, *M/A-COM: Tyco |
|
8.9
|
Low
Damage Dielectric Etching on GaAs Using a Helicon Wave High Density
Source
F.S. Pool, W.A. Wohlmuth, E. Maxwell, B.
Berggren, S. Roadman, S. Mahon, B. Howell and W. Mickanin, TriQuint
Semiconductor |
|
8.10
|
Improved
Plasma Etch Process Control of TiWN Gate
Length
Jason Fender, Susan
Chorrushi-Patino, Janet Hill-Tinkler,
Compound Semiconductor-1 Motorola, Inc. |
|
8.11
|
Life
Tests and TDDB Life Prediction Modeling of 50 nm Silicon Nitride
Capacitors
Gergana
I. Drandova, John M.
Beall, Kenneth D. Decker, Keith A.
Salzman,
TriQuint
Semiconductor |
|
8.12
|
Process
Optimization for 0.5 µm Dual Recess PHEMT Power Amplifiers
Sabyasachi
Nayak, Marcus King, Keith
Salzman, John Beall,
TriQuint
Semiconductor Texas |
|
8.13
|
Comparison of InAlAs/InP Hetero-interface Properties -MBE vs. MOCVD-
Misao Takakusaki, Hajime Momoi, Kouji Kakuta
and Hirofumi Nakata, Nikko Materials Co., Ltd. |
|
8.14
|
Development of High-Gain and High-Efficiency InGaP/GaAs HBT for
High-Voltage Operation
Yuefei Yang, Kevin Feng, Byounguk In, Chanh
Nguyen, Daniel Hou, Yaochung Chen and Dave Wang, Global
Communication Semiconductors, Inc. |
|
8.15
|
Strength
Improvement for the GaAs Thin Wafer
Hiep
Pham, Chang-Hwang Hua,
Skyworks
Solutions, Inc., |
|
8.16
|
Smooth,
Anisotropic Etching of Indium Containing Multi-layer Structures
Using a High Density ICP System
Yao-Sheng
Lee, Mike DeVre, David
Lishan, Brad Reelfs,
Russ Westerman,
Unaxis
USA, Inc. |
|
8.17
|
Yield
Enhancement Using Final Outgoing Automated Inspection System
Karen Lenaburg,
Susan Valocchi, Jan Campbell, Motorola,
Semiconductor Products Sector |
|
8.18
|
A
comparison of BCB with Polyimide process in manufacturing HBT
devices
June Nguyen, Oksun Dydasco, Harutoshi Saigusa,
Chang-Hwang Hua, Skyworks Solutions, Inc., |
|
8.19
|
Building
Solder Bumps on GaAs Flip Chip
Schottky Devices
Prasit
Sricharoenchaikit, M/A-COM, Inc., |
|
8.20
|
Stress
and Other Challenges with Evaporated Ni-Cr Thin Film Resistors Used
in the Manufacture of
ASICs
Necmi
Bilir and Long Do,
Skyworks
Solutions, Inc., |
|
8.21
|
Optical
Device Wafer Manufacturing in an IC Foundry
Sam Wang, Guojin Feng, Peter Lao, Sangmin Lee,
Sujane Wang, and Chanh Nguyen, Global Communication Semiconductors,
Inc. |
|
8.22
|
Improving process yield by utilizing smart SPC rules
Oded
Tal, MAX International Engineering Group |
|
8.23
|
High
Yield Lithography and Wafer Handling Methods for Reliable Backside
Processing of Brittle III-V Materials
C. Schaefer 1 , V.
Dragoi 1 , S.
Farrens 2 , M. Wimplinger , P.
Lindner 1, 1 EV Group E. Thallner GmbH,
2 EV Group Inc., |
|
8.24
|
An
InP/InGaAs SHBT Technology for
High-Speed Monolithic Optical Receivers
Shyh-Chiang
Shen, David C.
Caruth, Doris Chan, Aunt Thu, Jeffrey
Feng, and Milton Feng,
Xindium
Technologies, Inc. |
|
8.25
|
Advanced
Commercial InP
HBT IC Process
N. X. Nguyen, J. Fierro,
K. T. Feng, and C. Nguyen,
Global Communication
Semiconductors, Inc. |
|
8.26
|
Improved
characterization of diffusion in ohmic contacts using Backside SIMS
Patrick Van Lierde, Chunsheng Tian, Charles
Evans & Associates |
|
10.1
|
New
Manufacturing Concepts for Ultra-Thin Silicon and Gallium Arsenide
Substrates
K. Bock, M. Bleier, O. Köthe, C. Landesberger,
Fraunhofer Institute for Reliability and Microintegration IZM-M,
Munich branch of the institute, |
|
10.2
|
A Novel
Backside Process to Achieve 1-mil Thick Wafers at 6-inch Foundry
H.C. Chou, T.C. Lee, S.J. Huang, H.H. Weng,
M.H. Tsai, J.M. Lee, M. Chertouk, D.W. Tu, P.C. Chao, and C.S. Wu,
WIN Semiconductors Corporation |
|
10.3
|
Impact
of Backside Via Dimension Changes on High
Frequency GaAs MMIC Circuit Performance
P. Nam, R. Tsai, D. Davison, B. Allen, M.
Barsky, R.
Grundbacher, R. Lai and S. Olson, Northrop Grumman Space
Technology |
|
10.4
|
Dry
Etching of Deep Backside Vias in
InP
Maria Huffman
1, Timothy Engel 1, Nicholas
Pfister 1, Gabriel
Arevalo 1, Tom Brown 1, Maya Farhoud
1, Ron Miller 1, Ben
Keppeler 1, John Staroba 1,
Richard Jefferies 2 ., 1 Agilent
Technologies Inc., 2 Trikon
Technologies Ltd., |
|
10.5
|
Eliminating Pillars During GaAs Via Etch Formation
R. Westerman 1 , D. Johnson 1 , F. Clayton 2,
Unaxis USA, Inc., Motorola Inc., |
|
10.6
|
Optimization of Metal Adhesion for GaAs
Backside Wafer Processing
Terry Daly, Jason Fender, Bob
Duffin, Mike Kottke,
Compound Semiconductor-1 Motorola, Inc. |
|
11.1
|
Activities of Indium Phosphide in Japan
Yasuyuk
i Miyamoto, Department of Physical
Electronics, Tokyo Institute of Technology |
|
11.2
|
The
Emergence of SiGe:C HBT Technology for RF Applications
V. Ilderem, S.G. Thomas, J.P. John, S. Wipf,
D. Zupac, H. Rueda, F. Chai, R. Reuter*, J. Kirchgessner, J.Teplik,
P. Wennekers*, T. Baker, M. Clifford, J. Griffiths, M. Tawney, M.
McCombs, Digital DNA TM Laboratories, Semiconductor Products Sector,
*EMEA-Berlin, Motorola Inc, |
|
| 11.3 |
Investigation of stressing InP/InGaAs DHBTs under high current
density
V.E. Houtsma, J. Frackoviak, R.F. Kopf, R.R.
Reyes, W. Sung, A. Tate, Y. Yang, N.G. Weimann, and Y.K. Chen, Bell
Labs, Lucent Technologies |
Abstract |
| 11.4 |
GaInP/GaInAsN/GaAs
N-p-N Bipolar Transistors: Influence of Base Layer Composition and
Alloy Grading on Device Performance
Bryan D. Dickerson, Bradley J. Heath, and
Louis J. Guido,
Virginia Tech, Department of
Material Science and Engineering,
Kevin S. Stevens,
Charles R. Lutz, Eric M. Rehder, and
Roger E. Welser,
Kopin
Corporation, |
Abstract |
| 12.1 |
In-Line
Defectivity Methodology for a GaAs Manufacturing Facility
Jan Campbell, Karen Lenaburg, Niki Liggins,
Motorola, Semiconductor Product Sector |
Abstract |
| 12.2 |
High
uniformity, highly reproducible non-selective wet
gate
recess etch process for InP
HEMTs
Xin
Cao, Iain Thayne,
Ultrafast
Systems Group, Department of Electronics and Electrical Engineering,
University of Glasgow |
Abstract |
| 12.3 |
A High
Performance and High Yield Self-Aligned and Double Recessed
pHEMT Process with One Lithography Step
for Both Gate and First Recess Definition
Kamal
Tabatabaie-Alavi, Colin Whelan, and Elsa
Tong, Raytheon RF Components Company |
Abstract |
| 12.4 |
Electrophoretic Photoresist Application for High Topography Wafer
Surfaces
James Tajadod, Henry Hendriks, John Klocke*,
Antonio Morales, and Heather Rapuano, M/A-COM: Tyco |
Abstract |
| 12.5 |
Advances
in CPL, Collimated Plasma Source & Full Field Exposure for Sub-100nm
Lithography
Brent Boerger,
Scott Mcleod, Richard
Forber, I.C.E.
Turcu, Cel
Gaeta,
Donald K. Bailey, Jacob Ben-Jacob, JMAR Systems |
Abstract |
| 13.1 |
Ti/Al/Ni/Au
Ohmic Contacts on AlGaN/GaN HEMTs
A. Crespo, R. Fitch, J. Gillespie, N. Moser,
G. Via, M. Yannuzzi, Sensors Directorate, Air Force Research
Laboratory, Wright-Patterson AFB |
Abstract |
| 13.2 |
AlGaN/GaN
HEMTs on Silicon Carbide Substrates
for
Microwave Power Operation
Richard Lossy
1, Nidhi
Chaturvedi 1 , Peter
Heymann 1, Klaus
Köhler 2, Stefan Müller 2 and
Joachim Würfl , 1 Ferdinand-Braun-Institut
für
Höchstfrequenztechnik |
Abstract |
| 13.3 |
GaN-HEMT
on 100mm Diameter Sapphire Substrate Grown by MOVPE
Yohei
Otoki, *Michio
Kihara, *Takeshi Tanaka, *Kazuto Takano,
**Toshihide Kikkawa
and ***Tsutomu Igarashi, Semiconductor Engineering Dept., Hitachi
Cable, *Advanced Research Center, Hitachi Cable, **Fujitsu
Laboratories Ltd, ***Fujitsu Quantum Devices Ltd. |
Abstract |
| 13.4 |
Transition of High Power SiC
MESFETs from 2-inch to 3-inch Production
for Improved Cost and
Producibility
J.W. Milligan, S.T. Allen, J.J.
Sumakeris, A.R. Powell, J.R. Jenny, and
J.W. Palmour, Cree, Inc., |
Abstract |
| 13.5 |
Solid-State Lighting: Lamp Targets and Implications for the
Semiconductor Chip
Jeff Y. Tsao,
Sandia
National Laboratories |
Abstract |
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