Improving the Breakdown Voltage for 100nm GaAs pHEMTs by the Support of Device Simulations

P. Abele, M. Schaefer*1, M. Hosch *2, J. Splettstoesser, and D. Behammer

United Monolithic Semiconductors – GmbH, Wilhelm-Runge-Strasse 11, D-89081 Ulm, Germany
Phone: +49-731-505-3093, Fax: +49-731-505-3005, E-mail: abele@ums-ulm.de *1 CADwalk, Engineering Office Heinrich Walk, Stegaeckerstrasse 7, D-89604 Allmendingen, Germany
*2 Now with University of Ulm, Department of Electron Devices and Circuits, Albert-Einstein-Allee 45, D-89081 Ulm, Germany
Keywords: GaAs, pHEMT, device simulations, sub-threshold, leakage current, breakdown voltage, buffer, epitaxy
Abstract

In this work we discuss for a 100nm gate length GaAs pHEMT transistor with a transconductance of gmax=760mS/mm and an input capacitance of cin=740fF/mm the influence of the distance between the channel and super lattice on the drain leakage current Id and the breakdown voltage Vbds and the relation between both parameters. The understanding of this relation was possible by the help of device simulations. An improvement of 20% in the breakdown voltage Vbds was possible by optimizing the distance between channel and super lattice while the other process parameters were kept the same.
 
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